1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method of fabricating a floating gate of a flash memory cell using a sidewall process.
2. Background of the Related Art
Generally, a flash memory cell having an EEPROM (electrically erasable programmable read-only memory) tunnel oxide structure comprises a floating gate which is formed over an active area of a semiconductor substrate and is electrically isolated from the semiconductor substrate by a gate oxide layer, where the substrate has device on formed thereon, a control gate which is formed over the floating gate and is electrically isolated from the floating gate by a dielectric layer, and a source/drain region which is formed at both sides of the floating gate on the semiconductor substrate. The device isolation structure is made by a shallow trench isolation (STI) process or LOCOS (local oxidation of silicon) process.
Conventional technology forms a nitride capping layer as a hard mask by using bottom, anti-reflective coating and then performs a polysilicon etching process to fabricate a floating gate because of a difference in height between a field region and a moat region and bad reflection characteristics of a polysilicon layer. The technology has difficulty in controlling a critical dimension (CD), and causes excessive polysilicon loss while etching the nitride capping layer. Moreover, the excessive polysilicon loss may cause a bad profile and a moat pit in a later polysilicon etching process.
FIG. 1 illustrates, in a cross-sectional view, the structure of a flash memory device according to the conventional technology. As shown in FIG. 1, the conventional flash memory device comprises at least one floating gate 1 formed over a substrate, a control gate 2 covering the floating gate 1, and select gates 3, which are positioned on both sides of the control gate 2. One control gate operates two transistors, which increases the size of a cell device.
U.S. Pat. No. 6,605,506 to Wu discloses a method of fabricating a scalable stacked-gate flash memory device and its high-density memory arrays. The method uses four different spacer techniques to fabricate a scalable stacked-gate flash memory device. The first spacer technique is used to form buffer-oxide spacers. The second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using an STI structure. The third spacer is used to define the gate length of a scalable stacked-gate structure. The fourth spacer technique is used to form the sidewall spacers for self-aligned source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts.
U.S. Pat. No. 6,501,125 to Kobayashi describes a method of manufacturing a semiconductor device which can solve the problem that a memory cell size determines a write/erase speed of memory cell transistors and can increase the write/erase speed without the reduction in the reliability of an insulating film between a control gate and a second-layer floating gate.
U.S. Pat. No. 6,261,903 to Chang et al. provides a integrated circuit device having a flash memory cell. In Chang et al., the flash memory cell has a tunnel dielectric layer overlying a surface of a semiconductor substrate and a floating gate layer defined overlying the tunnel dielectric layer. The gate layer has an edge and a sidewall spacer extends along and on the edge. The combination of the sidewall spacer and the gate layer provide a surface for increasing gate coupling ratio.
U.S. Pat. No. 5,702,965 to Kim discloses a split-gate type flash memory cell with an insulation spacer of ONO (oxide-nitride-oxide) or ON (oxide-nitride) structure formed at the sidewalls of the floating gate. The cell is said to improve program and erasure capabilities of the cell by preventing reduction of the coupling ratio and leakage of electrons through the floating gate and the control gate.